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1 ? fn7510.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2008. all rights reserved. all other trademarks mentioned are the property of their respective owners. isl59450 multiformat video crosspoint with integrated sync separator the isl59450 is a video crosspoint switch supporting multiple video input formats (cvbs, s-video, ypbpr, and rgb signals). embedded anti-aliasing filters with programmable corner frequencies eliminate glitch noise from video dacs. the large number of inputs, wide range of formats, integrated anti -aliasing filters, and dual sync-separators make the isl59450 an ideal choice for video switching in near ly all display systems. the isl59450 is available in a 128 ld mqfp package and is specified for operation over the full -40c to +85c temperature range. simplified block diagram features ? 6 composite, 4 s-video and 4 component video sources ? 2 component inputs can be configured for vga with separate h and v sync inputs ? multi-format video filtering ? compatible with macrovision? encoded signals ? programmable gain of x1 or x2 ? outputs have high impedance disable mode ? two universal sync separators support sd, hd, and computer signals ? pb-free (rohs compliant) applications ? av receivers ?lcd-tvs ? av switch boxes ?projectors ? hdtv systems ? multiple video input systems ordering information part number (note) part marking package (pb-free) pkg. dwg. # ISL59450IQZ ISL59450IQZ 128 ld mqfp mdp0055 note: these intersil pb-free pl astic packaged products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. cvbs in 1 dc restore cvbs in 0 cvbs in 3 cvbs in 2 cvbs in 5 cvbs in 4 lpf lpf x1 x2 x1 x2 cvbs out a cvbs out b dc restore svideo in 0 lpf lpf x1 x2 x1 x2 svideo out a svideo out b svideo in 1 svideo in 2 svideo in 3 dc restore ypbpr in 0 lpf lpf x1 x2 x1 x2 ypbpr out a ypbpr out b ypbpr in 1 ypbpr in 2 ypbpr in 3 2 2 2 2 3 3 3 3 3 3 2 2 sync processor a vsync in a hsync in a vsync out a hsync out a sogs from video inputs sync processor b vsync in b hsync in b vsync out b hsync out b i2c system control scl sda data sheet february 14, 2008 n o t r e co m m e nd e d f o r ne w d e s i g ns n o re c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - int e r s i l o r w w w . i n t e r s il . c o m / t s c
2 fn7510.0 february 14, 2008 absolute maximum rati ngs thermal information voltage on v a (referenced to gnd = gnd a = gnd d ) . . . . . . . . . . . . . . . . . 6.0v voltage on v d (referenced to gnd = gnd a = gnd d ) . . . . . . . . . . . . . . . . . 4.0v voltage on any analog input pin . . . . . . . . . . . . . -0.3v to v a + 0.3v voltage on any digital input pin . . . . . . . . . . . . . . -0.3v to v d + 0.3v current into any output pin . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma esd classification human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000v machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125v thermal resistance ja (c/w) mqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.84 maximum biased junction temperature . . . . . . . . . . . . . . . . +150c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions temperature (commercial) . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . v a = 5.0v, v d = 3.3v caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a ac electrical specifications v a = 5.0v, v d = 3.3v, v in = 0.7v p-p , t a = +25c, r l = 150 , v tip inx = 0.5v, vslice inx = 0.6v, v luma x1 inx = v luma x2 inx = 0.8; v chroma x1 inx = v chroma x2 inx = 1.15v, all frequency response measurements relative to f = 100khz, unless otherwise specified. parameter description conditions min typ max unit ypbpr/rgb (component) video inputs ypbpr-10mhz passband flatness, 10mhz filter f = 6mhz, gain 1 -1.6 -1.1 -0.4 db f = 6mhz, gain 2 -1.6 -1.1 -0.4 db cutoff flatness, 10mhz filter f = 10mhz, gain 1 -4.2 -2.7 -1.5 db f = 10mhz, gain 2 -4.2 -2.7 -1.5 db stopband rejection, 10mhz filter f = 27mhz, gain 1 -30 -19 -11 db f = 27mhz, gain 2 -30 -19 -11 db f = 54mhz, gain 1 -51 db f = 54mhz, gain 2 -51 db ypbpr-20mhz passband flatness, 20mhz filt er f =12mhz, gain 1 -1.5 -0.9 -0.4 db f =12mhz, gain 2 -1.5 -0.9 -0.4 db cutoff bandwidth, 20mhz filter f = 20mhz, gain 1 db -3.6 -2.3 -1.3 f = 20mhz, gain 2 -3.6 -2.3 -1.3 db stopband rejection, 20mhz filter f = 54mhz, gain 1 -30 -15 -9 db f = 54mhz, gain 2 -30 -15 -9 db ypbpr-36mhz passband flatness, 36mhz filter f = 20mhz, gain 1 -1.6 -1 -0.4 db f = 20mhz, gain 2 -1.6 -1 -0.4 db cutoff bandwidth, 36mhz filter f = 36mhz, gain 1 -4.7 -2.7 -1.5 db f = 36mhz, gain 2 -4.7 -2.7 -1.5 db stopband rejection, 36mhz filter f = 108mhz, gain 1 -22 db f = 108mhz, gain 2 -22 db isl59450
3 fn7510.0 february 14, 2008 ypbpr-bypass passband flatness, filter bypassed f = 220mhz, gain 1 1 db f = 220mhz, gain 2 1 db cutoff bandwidth, filter bypassed gain 1 275 mhz gain 2 275 mhz positive slew rate, filter bypassed v out = 2v p-p, gain 1 350 450 v/s v out = 2v p-p, gain 2 450 590 v/s negative slew rate, filter bypassed v out = 2v p-p, gain 1 350 440 v/s v out = 2v p-p, gain 2 720 950 v/s s-video video inputs sv-10mhz passband flatness, 10mhz filter f =7mhz, gain 1 -2.3 -1.5 -0.8 db f =7mhz, gain 2 -2.3 -1.5 -0.8 db cutoff rejection, 10mhz filter f = 11mhz, gain 1 -5.5 -3.4 -2 db f = 11mhz, gain 2 -5.5 -3.4 -2 db stopband rejection, 10mhz f = 27mhz, gain 1 -32 -21 -11 db f = 27mhz, gain 2 -32 -21 -11 db sv-bypass passband flatness, filter bypassed f = 27mhz, gain 2 -2.3 -1 -0.8 db cutoff rejection, filter bypassed f = 54mhz, gain 2 -12 -3.6 -2.5 db cvbs (composite) video inputs cvbs-7mhz passband flatness, 7mhz filter f = 5mhz, gain 1 -2.7 -1.7 -1 db f = 5mhz, gain 2 -2.7 -1.7 -1 db cutoff rejection, 7mhz filter f = 7mhz, gain 1 -5 -3.2 -1.8 db f = 7mhz, gain 2 -5 -3.2 -1.8 db stopband rejection, 7mhz filter f = 27mhz, gain 1 -50 -39 -26 db f = 27mhz, gain 2 -50 -39 -26 db cvbs-bypass passband flatness, filter bypassed f = 27mhz, gain 2 -1.9 -1.1 -0.7 db cutoff rejection, filter bypassed f = 54mhz, gain 2 -7.2 -3.8 -2.7 db dg differential gain f = 3.58mhz, gain 1 0.5 % f = 3.58mhz, gain 2 0.3 % dp differential phase f = 3.58mhz, gain 1 0.45 f = 3.58mhz, gain 2 0.65 all video inputs inter-x talk inter-channel crosstalk any input of channel a to any output channel b and vice-versa, gain 1 and 2, f = 10mhz 85 db ac electrical specifications v a = 5.0v, v d = 3.3v, v in = 0.7v p-p , t a = +25c, r l = 150 , v tip inx = 0.5v, vslice inx = 0.6v, v luma x1 inx = v luma x2 inx = 0.8; v chroma x1 inx = v chroma x2 inx = 1.15v, all frequency response measurements relative to f = 100khz, unless otherwise specified. (continued) parameter description conditions min typ max unit isl59450
4 fn7510.0 february 14, 2008 dc electrical specifications v a = 5.0v, v d = 3.3v, t a = +25c, r l = 150 , v tip inx = 0.5v, vslice inx = 0.6v, v luma x1 inx = v luma x2 inx = 0.8; v chroma x1 inx = v chroma x2 inx = 1.15v, unless otherwise specified. parameter description conditions min typ max unit v a analog supply range 4.5 5.5 v v d digital supply range 2.7 3.6 v i a analog supply current all output groups enabled 290 350 ma 1 composite output enabled 25 ma 1 s-video output group enabled 48 ma 1 component output group enabled 75 ma i d digital supply current both sync separators enabled 3.5 6 ma i disabled standby supply current disabled analog current, i a 0.7 3 ma disabled digital current, i d 0.7 2.5 ma psrr power supply rejection gain 1 or 2, any output 50 db psrr clamp_on rejection with clamp enabled gain 1 or 2 45 db gain low frequency gain gain 1 0.95 1 1.05 v/v gain 2 1.9 2.0 2.1 v/v v os-clamp clamp offset (delta between external reference voltage and output during clamp) v ref = any reference input, gain 1 v ref - 30mv v ref + 30mv mv v ref = any reference input, gain 2 v ref - 30mv v ref + 30mv mv v os v in - v out (useful if dc-coupling) clamp disabled, a v = 1 0.45 v i pulldown input pulldown current v in = 2v, clamp enabled (sinking) 1 a i clamp clamp pullup current cv and s-video, normal offset mode, clamp enabled (sourcing) 100 130 170 a component/rgb, normal offset mode, clamp enabled (sourcing) 220 270 320 a cv and s-video, low offset mode, clamp enabled (sourcing) 220 270 320 a component/rgb, low offset mode, clamp enabled (sourcing) 400 500 650 a i sc short circuit current vin = 3v, av2 = 2.0v, sourcing, r l = 10 to gnd 60 102 140 ma vin = 0v, sinking, r l = 10 to +3v 20 30 40 ma v out-lin output linear voltage range 0.5 2.5 v logic inputs (sda, scl, address, reset, powerdown, hsync inx , vsync inx , sdetx) v ih input high voltage (high) all logic pins, except reset 2v reset (pin must be >3.5v to ensure part is not resetting) 3.5 v v il input low voltage (low) 0.8 v i ih input high current (v in = 5v, logic inputs, sinking) no pull-up or pull-down -1 0 1 a pins with 300k internal pull-downs: address, reset , power-down 81734a i il input low current (v in = 0v, logic inputs, sourcing) no pull-up or pull-down -1 0 1 a pins with 300k internal pull-up: sdetx 10 15 25 a isl59450
5 fn7510.0 february 14, 2008 i 2 c timing diagram serial interface (i 2 c) specifications symbol parameter conditions min (note 1) typ max (note 1) unit v ol sda output buffer low voltage i ol =4ma 0 0.4 v i li input leakage current on scl v in = 5.5v 0.1 1 a i lo i/o leakage current on sda v in = 5.5v 0.1 1 a timing characteristics f scl scl frequency 400 khz t low clock low time measured at the 30% of v d crossing. 1.3 s t high clock high time measured at the 70% of v d crossing. 0 0.9 s t su:sta start condition set-up time scl rising edge to sda falling edge. both crossing 70% of v d . 0.6 s t hd:sta start condition hold time from sda falling edge crossing 30% of v d to scl falling edge crossing 70% of v d . 0.6 s t hd:dat input data hold time from scl falling edge crossing 70% of v d to sda entering the 30% to 70% of v d window. 00.9s t su:sto stop condition set-up time from scl rising edge crossing 70% of v d , to sda rising edge crossing 30% of v d 0.6 s t r sda and scl rise time from 30% to 70% of v d 20 + 0.1 x cb ns t f sda and scl fall time from 70% to 30% of v d 20 + 0.1 x cb ns cb capacitive loading of sda or scl total on-chip and off-chip 400 pf cpin sda and scl pin capacitance 10 pf note: 1. parts are 100% tested at +25c. temperature limits established by characterization and are not production tested. t su:sto t high t su:sta t hd:sta t hd:dat scl sda (input timing) sda (output timing) t f t low t r isl59450
6 fn7510.0 february 14, 2008 functional diagram y in 0 pr in 0 pb in 0 y in 1 pr in 1 pb in 1 y in 2 pr in 2 pb in 2 y in 3 pr in 3 pb in 3 component channel a sy in 0 sc in 0 sy in 1 sc in 1 sy in 2 sc in 2 sy in 3 sc in 3 s-video channel a cv in 1 cv in 0 cv in 3 cv in 2 cv in 5 cv in 4 composite channel a sync separator a hsync in a vsync in a v d = 3.3v gnd d v a = 5.0v v a = 5.0v v a = 5.0v i 2 c interface gnd gnd gnd hsync out a vsync out a clamp out a sync y-c sync cv sync comp. y out a pb out a pr out a sy out a sc out a cv out a v d = 3.3v gnd d field out a y in 0 pr in 0 pb in 0 y in 1 pr in 1 pb in 1 y in 2 pr in 2 pb in 2 y in 3 pr in 3 pb in 3 component channel b sy in 0 sc in 0 sy in 1 sc in 1 sy in 2 sc in 2 sy in 3 sc in 3 s-video channel b cv in 1 cv in 0 cv in 3 cv in 2 cv in 5 cv in 4 composite channel b sync separator b v d = 3.3v gnd d v a = 5.0v v a = 5.0v v a = 5.0v gnd gnd gnd hsync out b vsync out b clamp out b y out b pb out b pr out b sy out b sc out b cv out b field out b hsync in b vsync in b sda scl address reset keyed clamp timing (slave mode) keyed clamp timing (slave mode) digital control signals sync comp. sync y-c sync cv isl59450
7 fn7510.0 february 14, 2008 component block diagram v tip v lumax1 clamp (from sync sep.) v lumax2 v slice sync timing (to sync separator) y out y in0 + - v os 1 0 + - + - x1 x2 slicer component control register bits 1:0 00 01 10 11 1,1 1,0 0,x component control register bits 7, 4 y in1 y in2 y in3 v chromax1 v chromax2 pr out + - v os 1 0 clamp from sync separator x1 x2 + - component control register bits 6, 4 pr in0 component control register bits 1:0 00 01 10 11 pr in1 pr in2 pr in3 component control register bit 7 pb out + - v os 1 0 clamp from sync separator x1 x2 + - pb in0 component control register bits 1:0 00 01 10 11 pb in1 pb in2 pb in3 component control register bit 7 0,0 0,1 1,1 1,0 v lumax1 v lumax2 v chromax1 v chromax2 component control register bits 6, 4 0,0 0,1 1,1 1,0 v lumax1 v lumax2 component control register bit 7 lpf lpf lpf component control register bits 3:2 component control register bits 3:2 component control register bits 3:2 1 a 1 a 1 a isl59450
8 fn7510.0 february 14, 2008 s-video block diagram composite block diagram v tip v lumax1 clamp (from sync sep.) v lumax2 v slice sy out sy in0 + - v os 1 0 + - + - x1 x2 slicer s-video control register bits 1:0 00 01 10 11 1,1 1,0 0,x s-video control register bits 7, 4 sy in1 sy in2 sy in3 v chromax1 v chromax2 sc out + - v os 1 0 clamp from sync separator x1 x2 + - s-video control register bit 4 0 1 sc in0 s-video control register bits 1:0 00 01 10 11 sc in1 sc in2 sc in3 s-video control register bit 7 s-video control register bit 7 sync timing (to sync separator) lpf s-video control register bit 3 lpf s-video control register bit 3 1 a 1 a v tip v lumax1 v lumax2 v slice cv out cv in0 + - v os 1 0 + - + - x1 x2 slicer composite control register bits 2:0 000 001 010 011 100 101 1,1 1,0 0,x composite control register bits 7, 4 cv in1 cv in2 cv in3 cv in4 cv in5 clamp (from sync sep.) sync timing (to sync separator) lpf composite control register bit 3 1 a composite control register bit 7 isl59450
9 fn7510.0 february 14, 2008 sync separator block diagram sync separator sync from composite slicer hsync in vsync in h v h v sync separator control bits 1:0 sync separator control bit 2 10 01 00 11 1 0 10 sync separator enable (bit 5) hsync in sync from s-video slicer sync from component slicer fieldout 0 1 hsync out vsync out sync separator control bit 7 sync separator control bits 3:0 keyed clamp timing signal (to all channels) 1011 all other settings clampout isl59450
10 fn7510.0 february 14, 2008 typical application circuit cv in 0 cv in 1 cv in 2 cv in 3 cv in 4 cv in 5 75 + 0.1f 75 0.1f 75 + 0.1f 75 + 0.1f 75 + 0.1f 75 + 0.1f 75 + 0.1f 75 + 0.1f sy in 0 sc in 0 isl59450 sy in 3 sc in 3 sy in 2 sc in 2 sy in 1 sc in 1 75 + 0.1f 75 + 0.1f 75 + 0.1f 75 + 0.1f 75 + 0.1f 75 + 0.1f 75 + 0.1f 75 + 0.1f y in 2 pb in 2 pr in 2 75 + 0.1f 75 + 0.1f 75 + 0.1f y in 1 pb in 1 pr in 1 75 + 0.1f 75 + 0.1f 75 + 0.1f y in 0 pb in 0 pr in 0 75 + 0.1f 75 + 0.1f 75 + 0.1f y in 3 pb in 3 pr in 3 75 + 0.1f 75o + 0.1f 75 + 0.1f hsync in a vsync in a hsync in b vsync in b cv out a cv out b sy out a sc out a sy out b sc out b y out a pr out a pb out a y out b pr out b pb out b sda scl address powerdown reset vtip in a vtip in b v chroma x2 in a v chroma x1 in a vslice in a vslice in b v chroma x2 in b v chroma x1 in b v luma x2 in a v luma x1 in a v luma x2 in b v luma x1 in b 0.5v 0.6v 1v v a v d gnd 75 75 75 75 75 75 c 0.01f 1f +5v 0.01f 1f +3.3v 75 75 75 hsync out a vsync out a hsync out b vsync out b composite 1 composite 2 composite 3 composite 6 composite 5 composite 4 75 75 75 s-video luma 1 s-video chroma 1 component luma 1 component pb 1 component pr 1 component luma 2 component pb 2 component pr 2 green 1 (sog) blue 1 red 1 s-video luma 2 s-video chroma 2 s-video luma 3 s-video chroma 3 s-video luma 4 s-video chroma 4 green 2 blue 2 red 2 hsync 2 vsync 2 s-video out s-video out vga out hd out 0.1f 0.1f 56nf 56nf c set ac set b 0.1f isl59450
11 fn7510.0 february 14, 2008 pinout isl59450 (128 ld mqfp) top view 2 1 3 4 5 6 7 8 9 10 12 11 13 14 15 16 17 18 19 20 23 22 24 25 26 27 28 29 30 31 33 32 34 35 36 37 38 21 39 40 41 42 43 44 45 46 47 49 48 50 51 52 53 54 55 56 57 60 59 61 62 63 64 58 101 102 100 99 98 97 96 95 94 93 91 92 90 89 88 87 86 85 84 83 80 81 79 78 77 76 75 74 73 72 70 71 69 68 67 66 65 82 103 104 105 106 107 108 109 110 111 113 112 114 115 116 117 118 119 120 121 124 123 125 126 127 128 122 clamp out a dnc gnd d gnd d hsync in a vsync in a c set a gnd d gnd d v d gnd d gnd d gnd d vtip in a vslice in a v luma x1 in a v luma x2 in a v chroma x1 in a v chroma x2 in a v a gnd a gnd a cv in 0 cv in 1 gnd a clamp out b dnc gnd d gnd d gnd d hsync in b vsync in b c set b gnd d gnd d gnd d v d gnd d gnd d vtip in b vslice in b v chroma x1 in b gnd a gnd a v a gnd a cv in 5 cv in 4 v chroma x2 in b sdet0 cv in 2 sy in 0 sc in 0 sdet1 sy in 1 sc in 1 gnd a y in 0 pb in 0 gnd a pr in 0 y in 1 gnd a pb in 1 pr in 1 gnd a v a gnd a v a gnd a y in 2 pb in 2 pr in 2 gnd a y in 3 gnd a pb in 3 pr in 3 sdet2 sc in 2 sy in 2 sdet3 sy in 3 sc in 3 gnd a cv in 3 gnd a vsync out a field out a hsync out a v d gnd a gnd a cv out a gnd a sy out a sc out a y out a address pb out a pr out a v a gnd d sda gnd d v d v a gnd a pr out b pb out b y out b gnd d sc out b sy out b gnd a gnd a cv out b gnd a v d hsync out b vsync out b field out b scl gnd d v luma x1 in b v luma x2 in b reset powerdown isl59450
12 fn7510.0 february 14, 2008 pin descriptions pin number pin name description composite (cv) video inputs (6x1) 127 cv in 0 composite video input 0 128 cv in 1 composite video input 1 1cv in 2 composite video input 2 38 cv in 3 composite video input 3 39 cv in 4 composite video input 4 40 cv in 5 composite video input 5 composite (cv) video outputs 96 cv out a composite video output a with high-z disable mode 71 cv out b composite video output b with high-z disable mode s-video (sv) inputs (4x2) 3sy in 0 s-video luma input 0 4sc in 0 s-video chroma input 0 6sy in 1 s-video luma input 1 7sc in 1 s-video chroma input 1 32 sy in 2 s-video luma input 2 33 sc in 2 s-video chroma input 2 35 sy in 3 s-video luma input 3 36 sc in 3 s-video chroma input 3 s-video (sv) outputs 94 sy out a s-video luma output a with high-z disable mode 93 sc out a s-video chroma output a with high-z disable mode 73 sy out b s-video luma output b with high-z disable mode 74 sc out b s-video chroma output b with high-z disable mode s-video connection detection pins 2 sdet0 digital input with internal pull-up to v a . detects s-video connector 0. tie to nc switch on s-video connector, with other end of switch tied to ground. 0v = no cable attached, v a = s-video cable attached. 300k pull-up to analog supply. 5 sdet1 digital input with internal pull-up to v a . detects s-video connector 1. tie to nc switch on s-video connector, with other end of switch tied to ground. 0v = no cable attached, v a = s-video cable attached. 300k pull-up to analog supply. 31 sdet2 digital input with internal pull-up to v a . detects s-video connector 2. tie to nc switch on s-video connector, with other end of switch tied to ground. 0v = no cable attached, v a = s-video cable attached. 300k pull-up to analog supply. 34 sdet3 digital input with internal pull-up to v a . detects s-video connector 3. tie to nc switch on s-video connector, with other end of switch tied to ground. 0v = no cable attached, v a = s-video cable attached. 300k pull-up to analog supply. component (ypbpr) video inputs (4x3) 9y in 0 luma component (or green rgb) video input 0 10 pb in 0 chroma pb component (or blue rgb) video input 0 11 pr in 0 chroma pr component (or red rgb) video input 0 13 y in 1 luma component (or green rgb) video input 1 15 pb in 1 chroma pb component (or blue rgb) video input 1 isl59450
13 fn7510.0 february 14, 2008 16 pr in 1 chroma pr component (or red rgb) video input 1 22 y in 2 luma component (or green rgb) video input 2 24 pb in 2 chroma pb component (or blue rgb) video input 2 25 pr in 2 chroma pr component (or red rgb) video input 2 27 y in 3 luma component (or green rgb) video input 3 29 pb in 3 chroma pb component (or blue rgb) video input 3 30 pr in 3 chroma pr component (or red rgb) video input 3 component video outputs 91 y out a component video luma output a with high-z disable mode 89 pb out a chroma pb component (or blue component) video output a with high-z disable 88 pr out a chroma pr component (or red component) video output a with high-z disable 76 y out b component video luma output b with high-z disable mode 78 pb out b chroma pb component (or blue component) video output b with high-z disable 79 pr out b chroma pr component (or red component) video output b with high-z disable a sync separator inputs and outputs 108 hsync in a horizontal external sync source for sync sepa rator a. this signal may be pure hsync or csync. 109 vsync in a vertical external sync source for sync separator a 110 c set a sync separator filter capacitor. connect a 0.056f capacitor between this pin and analog ground. 100 hsync out a horizontal sync output for sync separator a 101 vsync out a vertical sync output for sync separator a 102 field out a field flag for sync separator a. low = odd field, high = even field. 103 clamp out a external clamp timing pulse for sync se parator a (for timed back porch clamping) b sync separator inputs and outputs 59 hsync in b horizontal external sync source for sync sepa rator b. this signal may be pure hsync or csync. 58 vsync in b vertical external sync source for sync separator b 57 c set b sync separator filter capacitor. connect a 0.056f capacitor between this pin and analog ground. 67 hsync out b horizontal sync output from sync separator b 66 vsync out b vertical sync output from sync separator b 65 field out b field flag for sync separator b. low = odd field, high = even field. 64 clamp out b external clamp timing pulse for sync se parator b (for timed back porch clamping) external dc reference levels 122 v chroma x2 in a analog input. chroma reference level for dc-restore when a v = 2, for channel a. this dc voltage sets the midpoint voltage of the c signal (s-video) and the pb, pr signals (component video) for channel a when the gain is set to x2. when using the ypbpr inputs in ypbpr mode , this dc voltage sets the clamp voltage of the pr/r and pb/b signals for channel a. th is input is typically tied together with v chroma x2 in b and driven with the same voltage. 121 v chroma x1 in a analog input. chroma reference level for dc-restore when a v = 1, for channel a. this voltage sets the midpoint voltage of the c signal (s-video) and t he pb, pr signals (component video) for channel a when the gain is set to x1. when using the ypbpr inputs in ypbpr mode , this dc voltage sets the clamp voltage of the pr/r and pb/b signals for channel a. th is input is typically tied together with v chroma x1 in b and driven with the same voltage. pin descriptions (continued) pin number pin name description isl59450
14 fn7510.0 february 14, 2008 120 v luma x2 in a analog input. luma reference level for dc-restore when a v = 2, for channel a. when using the ypbpr inputs in rgb mode , this dc voltage sets the clamp voltage of the pr/r and pb/b signals for channel a when the gain is set to x2. when using the ypbpr inputs in ypbpr mode , this dc voltage sets the clamp voltage of the pr/r and pb/b signals for channel a. this input is typicall y tied together with v luma x2 in b and driven with the same voltage. the y/g signal is clamped to the vtip in a voltage in master mode and v luma x2 in a in slave mode. 119 v luma x1 in a analog input. luma reference level for dc-restore when a v = 1, for channel a. when using the ypbpr inputs in rgb mode , this dc voltage sets the clamp voltage of the r and b signals for channel a when the gain is set to x1. this input is typically tied together with v luma x1 in b and driven with the same voltage. the y/g signal is clamped to the vtip in a voltage in master mode and v luma x1 in a in slave mode. 118 vslice in a analog input. slicer comparator threshold for extracti ng composite sync from video, for channel a. this dc voltage is typically set to 0.07v above vtip in a, creating a sync tip slicing level of 70mv. this input is typically tied together with vslice in b and driven with the same voltage. 117 vtip in a analog input. sync tip reference level for dc-restore, for channel a. this dc voltage sets the level of the sync tip of channel a?s output signal. this input is typically tied together with vtip in b and driven with the same voltage. in rgb mode (with no sync-on-green ), this sets the black level of the g channel. 45 v chroma x2 in b analog input. chroma reference level for dc-restore when a v = 2, for channel a. this dc voltage sets the midpoint voltage of the c signal (s-video) and the pb, pr signals (component video) for channel a when the gain is set to x2. when using the ypbpr inputs in ypbpr mode , this dc voltage sets the clamp voltage of the pr/r and pb/b signals for channel b. th is input is typically tied together with v chroma x2 in a and driven with the same voltage. 46 v chroma x1 in b analog input. chroma reference level for dc-restore when a v = 1, for channel a. this voltage sets the midpoint voltage of the c signal (s-video) and t he pb, pr signals (component video) for channel a when the gain is set to x1. when using the ypbpr inputs in ypbpr mode , this dc voltage sets the clamp voltage of the pr/r and pb/b signals for channel b. th is input is typically tied together with v chroma x1 in a and driven with the same voltage. 47 v luma x2 in b analog input. luma reference level for dc-restore when a v = 2, for channel b. when using the ypbpr inputs in rgb mode , this dc voltage sets the clamp voltage of the r and b signals for channel b when the gain is set to x2. this input is typically tied together with v luma x2 in a and driven with the same voltage. the y/g signal is clamped to the vtip in b voltage in master mode and v luma x2 in b in slave mode. 48 v luma x1 in b analog input. luma reference level for dc-restore when a v = 1, for channel b. when using the ypbpr inputs in rgb mode , this dc voltage sets the clamp voltage of the r and b signals for channel b when the gain is set to x1. this input is typically tied together with v luma x1 in a and driven with the same voltage. the y/g signal is clamped to the vtip in b voltage in master mode and v luma x1 in b in slave mode. 49 vslice in b analog input. slicer comparator threshold for extracti ng composite sync from video, for channel b. this dc voltage is typically set to 0.07v above vtip in b, creating a sync tip slicing level of 70mv. this input is typically tied together with vslice in a and driven with the same voltage. 50 vtip in b analog input. sync tip reference level for dc-restore, for channel b. this dc voltage sets the level of the sync tip of channel b?s output signal. this input is typically tied together with vtip in a and driven with the same voltage. in rgb mode (with no sync-on-green ), this sets the black level of the g channel. i 2 c control and i/o 85 sda i 2 c bus data i/o 82 scl i 2 c bus clock 92 address digital input with internal pull-down. sets i 2 c address: 0x84 if tied low, 0x8c if tied high. (300k pull-down) ic reset, enable and misc. 77 reset 5v digital input, with 3.5v logic threshold and a 300k pull-down. tie to +5v for normal operation. taking reset to 0v and back to 5v initializes all data registers to 0x00. 90 powerdown digital input with 300k pull-down. when this pin is taken high, all analog circui try is disabled to minimize power consumption. in powerdown mode, the outputs are tri-stated while the i 2 c interface remains active and all register data is retained. power supplies 18, 20, 42, 125 v a +5v analog supply pin descriptions (continued) pin number pin name description isl59450
15 fn7510.0 february 14, 2008 80, 87 v a +5v analog supply for output drivers power supplies digital (3v) 83 v d digital plus supply for i 2 c 53, 68, 99, 114 v d digital supply for sync separators power supplies analog ground (0v) 8, 12, 14, 17, 19, 21, 23, 26, 28, 37, 41, 43, 44, 69, 70, 72, 81, 95, 97, 98, 123, 124, 126 gnd a analog ground power supplies digital ground (0v) 51, 52, 54, 55, 56, 60, 61, 62, 75, 84, 86, 105, 106, 107, 111, 112, 113, 115, 116 gnd d digital ground unused pins 63, 104 dnc not implemented. do not connect t hese pins to anything (leave floating). pin descriptions (continued) pin number pin name description typical performance curves v a = +5v, v d = +3.3v, r l = 150 to gnd, t a = +25c, unless otherwise specified. figure 1. analog supply current vs supply voltage figure 2. digital supply current vs supply voltages figure 3. composite frequency response (gain 1) figure 4. composite frequency response (gain 2) 272 273 274 275 276 277 278 279 280 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 voltage (v) supply current (ma) no input no load all outputs enabled 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 voltage (v) digital supply current (ma) no input no load both sync separator enabled -40 -35 -30 -25 -20 -15 -10 -5 0 5 0.1m 1m 10m 100m 1g frequency (hz) magnitude (db) v in = 700mv p-p filter enabled filter bypassed -21 -19 -17 -15 -13 -11 -9 -7 -5 -3 -1 1 3 0.1m 1m 10m 100m frequency (hz) magnitude (db) filter enabled filter bypassed v in = 700mv p-p isl59450
16 fn7510.0 february 14, 2008 figure 5. s-video frequency response (gain 1) figure 6. s-video frequency response (gain 2) figure 7. component bandwidth vs frequency response (gain = 1) figure 8. component bandwidth vs frequency response (gain = 2) figure 9. differential gain figure 10. differential phase typical performance curves v a = +5v, v d = +3.3v, r l = 150 to gnd, t a = +25c, unless otherwise specified. (continued) -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 0.1m 1m 10m 100m frequency (hz) magnitude (db) filter enabled filter bypassed v in = 700mv p-p -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 0.1m 1m 10m 100m magnitude (db) frequency (hz) v in = 700mv p-p filter enabled filter bypassed -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 0.1m 1m 10m 100m 1g frequency (hz) magnitude (db) component 10mhz component 20mhz component 36mhz component bypass v in = 700mv p-p -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 0.1m 1m 10m 100m 1g frequency (hz) magnitude (db) v in = 700mv p-p component 20mhz component 36mhz component bypass component 10mhz -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 output dc voltage (v) dg (%) gain 2 gain 1 v ac = 40mv p-p f = 3.58mhz composite output filter enabled -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1. 9 output dc level (v) dp () gain 1 gain 2 v ac = 40mv p-p f = 3.58mhz composite output filter enabled isl59450
17 fn7510.0 february 14, 2008 figure 11. colorbar response figure 12. 2t response figure 13. 12.5t response figure 14 . component large signal pulse response gain 1 figure 15. component large signal pulse response gain 2 figure 16. composite group delay typical performance curves v a = +5v, v d = +3.3v, r l = 150 to gnd, t a = +25c, unless otherwise specified. (continued) timebase = 10s/div input: 500mv/div output: 1v/div gain 2 filter enabled v tip = 0.5v composite input composite output timebase = 100ns/div input: 200mv/div output: 500mv/div gain 2 filter enabled v tip = 0.5v composite input composite output timebase = 500ns/div input: 200mv/div output: 500mv/div gain 2 filter enabled v tip = 0.5v composite input composite output f in = 10mhz timebase = 10ns/div verticle scale: 500mv/div component output f in = 10mhz timebase = 10ns/div verticle scale: 500mv/div component output 0 10 20 30 40 50 60 70 delay (ns) gain 1 and gain 2 0.1m 1m 10m 100m frequency (hz) v in = 700mv p-p isl59450
18 fn7510.0 february 14, 2008 figure 17. s-video group delay figure 18. component 10mhz filter group delay figure 19. component 20mhz filter group delay figure 20. component 36mhz filter group delay figure 21. component bypass group de lay figure 22. inter-channel crosstalk typical performance curves v a = +5v, v d = +3.3v, r l = 150 to gnd, t a = +25c, unless otherwise specified. (continued) 0 10 20 30 40 50 60 0.1m 1m 10m 100 m frequency (hz) delay (ns) gain 1 and gain 2 v in = 700mv p-p 0 5 10 15 20 25 30 35 40 45 delay (ns) 0.1m 1m 10m 100m frequency (hz) gain 1 gain 2 v in = 700mv p-p 0 5 10 15 20 25 delay (ns) 0.1m 1m 10m 100m frequency (hz) gain 1 gain 2 v in = 700mv p-p 0 2 4 6 8 10 12 14 16 18 delay (ns) gain 1 and gain 2 v in = 700mv p-p 0.1m 1m 10m 100m frequency (hz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.1m 1m 10m 100m 1g frequency (hz) delay (ns) gain 1 gain 2 v in = 700mv p-p -90 -85 -80 -75 -70 -65 -60 -55 -50 crosstalk (db) any input of channel a to any output channel b and vice-versa gain 1 and gain 2 0.1m 1m 10m 100 m frequency (hz) isl59450
19 fn7510.0 february 14, 2008 figure 23. intra-channel crosstalk: composite to component/s-video figure 24. intra-channel crosstalk: s-video to component/composite figure 25. intra-channel crosstalk: component input to composite output figure 26. intra-channel crosstalk: component input to s-video output figure 27. composite/s-video: clamp response to +250mv step on input (high offset mode) figure 28. composite/s-video: clamp response to +250mv step on input (low offset mode) typical performance curves v a = +5v, v d = +3.3v, r l = 150 to gnd, t a = +25c, unless otherwise specified. (continued) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 crosstalk (db) composite input to s-video output filter disabled composite input to s-video output filter enabled composite input to component output filter enabled composite input to component output filter disabled 0.1m 1m 10m 100m frequency (hz) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 crosstalk (db) s-video input to composite output filter disabled s-video input to composite output filter enabled s-video input to component output filter disabled s-video input to component output filter enabled 0.1m 1m 10m 100m frequency (hz) -90 -80 -70 -60 -50 -40 -30 -20 crosstalk (db) bypass mode 10mhz filter engaged 0.1m 1m 10m 100 m frequency (hz) 20mhz filter engaged 36mhz filter engaged -100 -90 -80 -70 -60 -50 -40 -30 -20 crosstalk (db) bypass mode 0.1m 1m 10m 100m frequency (hz) 20mhz filter engaged 36mhz filter engaged 10mhz filter engaged timebase = 500s/div input: 500mv/div output: 1v/div any filter setting gain 2 low offset bit = 0 input = video + 2hz square wave (before coupling capacitor) composite or s-video output timebase = 500s/div input: 500mv/div output: 1v/div any filter setting gain 2 low offset bit = 1 input = video + 2hz square wave (before coupling capacitor) composite or s-video output isl59450
20 fn7510.0 february 14, 2008 figure 29. component: clamp response to +250mv step on input (high offset mode) figure 30. component: clamp response to +250mv step on input (low offset mode) figure 31. pull-down current response figure 32. psrr vs frequency figure 33. package power dissipation typical performance curves v a = +5v, v d = +3.3v, r l = 150 to gnd, t a = +25c, unless otherwise specified. (continued) timebase = 500s/div input: 500mv/div output: 1v/div any filter setting gain 2 low offset bit = 0 input = video + 2hz square wave (before coupling capacitor) yprpb timebase = 500s/div input: 500mv/div output: 1v/div any filter setting gain 2 low offset bit = 1 input = video + 2hz square wave (before coupling capacitor) yprpb output timebase = 10ms/div input: 500mv/div output: 1v/div any filter setting gain 2 input = video + 2hz square wave (before coupling capacitor) any output -60 -50 -40 -30 -20 -10 1k 10k 100k 1m 10m frequency (hz) rejection (db) any output v ac = 200mv p-p 0 gain 1 gain 2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 ambient temperature (c) power dissipation (w) ja = +27.84c/w 128 ld mqfp isl59450
21 fn7510.0 february 14, 2008 functional description signal muxes the isl59450 accepts 6 composite, 4 s-video and 4 component video sources. each signal type is routed into a crosspoint mux with two outputs. the 6 composite signals are routed into a 6:2 mux, the s-video inputs are routed into a double 4:2 mux and the component video signals are routed into a triple 4:2 mux. each mux is controlled through the i 2 c interface. each signal type has two dedicated outputs, a and b. signal types cannot be routed to different signal type outputs. for example, an s-video signal (y, c) cannot be routed to the composite outputs. for the luma (y and cvbs) channels, the dc-restore function is either a standard syn c-tip clamp (master mode) or slaved to a clamp signal generated from the sync separator (slave mode). for the chroma (c and pr/pb) channels, the dc-restore function is a keyed clamp timed to the luma channel (master mode) or timed to a clamp signal generated from the sync separator (slave mode). the clamping circuit restores the ac-coupled video signal to a fixed dc level (v tip , or v luma ). the clamping circuit provides line-by-line restoration of the video sync level to a the selected dc reference voltage during the sync tip. clamp modes the isl59450 has two clamp modes: master and slave. each output group can operate in either mode. in master mode, sync timing is derived directly from the video signal and video levels are clamped using this internal sync signal. in slave mode, video sync is derived from the input groups corresponding sync separator (a or b) or an exte rnal source connected to the corresponding sync separator. in the slave mode, the sync timing can come from hsync in and vsync in or it can be derived from the sync timing on the active video on the composite, s-video, or com ponent channels (see ?sync separator block diagram? on page 9). in the slave mode, clamping occurs during the sync tip of the selected video signal or the hsync signal (external hsync input). filters the isl59450 has integrated an ti-aliasing/smoothing filters for sd and hd video signals. for the composite video signals, the user can use a 7mhz low pass filter or bypass it (40mhz bandwidth). s-video signals have an 10mhz filter with bypass (43mhz). compone nt video signals have a user-selectable 36mhz, 20mhz, or 10mhz filter, or bypass (275mhz). all filters selections are made via the i 2 c host interface. clamps the clamps for all the luma and composite channels can be sync tip clamps (master mode) or timed keyed clamps (slave mode) driven off the sync separator. the clamps for the chroma channels (c/pr/pb) are keyed clamps timed to either the luma (master mode) or the sync separator (slave mode). clamp disable the clamp can be disabled for each channel by setting the appropriate bit high in the miscellaneous 2 register (0x16). for the s-video and component channels, additional action needs to be taken in order to completely disable the clamps. for s-video, setting the bit in the miscellaneous 2 register disables the pull-down 1a pull-down current for both the luma and chroma channel along with the clamp pull-up current for the luma channel. however, it does not disable the clamp pull-up current for the chroma channel unless the sync separator for that c hannel is set to 0x25. for component, setting the bit in the miscellaneous 2 register disables the pull-down 1a pull-down current for all three channels, along with the clamp pull-up current for the luma channel. however, it does not disable the clamp pull-up current for the pr and pb channels unless the sync separator for that channel is set to 0x24. low offset mode setting bit 6 in the composite and s-video channel registers increases the maximum amount of pull-up clamp current available from 130a to 270a , which slightly reduces the offset between the reference a nd the output when the clamp is enabled. for the component channels, this setting can be enabled by setting bit 7 in the miscellaneous 2 register for channel a and bit 3 for channel b. this mode increases the maximum amount of pull-up clamp current available from 270a to 500a. references table 1 shows the references used for clamping depending on the mode and video input being used. v slice should usually be set to 70mv to 100mv above the selected reference leve l for luma. table 1. channel reference levels video output master mode slave mode gain 1 gain 2 gain 1 gain 2 composite v tip v tip v luma x1 v luma x2 s-video luma v tip v tip v luma x1 v luma x2 s-video chroma v chroma x1 v chroma x2 v chroma x1 v chroma x2 component: luma/green (yprpb mode) v tip v tip v luma x1 v luma x2 component: luma/green (rgb mode) v tip v tip v luma x1 v luma x2 isl59450
22 fn7510.0 february 14, 2008 bypass each reference voltage with a 0.01f capacitor to ground to reduce noise injection. outputs/levels each signal output has a selectable gain of 0db (gain 1) or 6db (gain 2). the input to the sync separators can be any of the video inputs, as shown in the ?sync separator block diagram? on page 9. the hsync and vsync inputs are dedicated to their respective sync separato r (i.e. sync separator a can connect to hsync in a and vsync in a, but not hsync in b and vsync in b). sync separators the isl59450 contains two high performance video sync separators that automatically lock to any sd and hd video signal. they will also extract sync timing information from non-standard video inputs and in the presence of macrovision pulses. composite sync, vertical sync and horizontal sync outputs are provided from each sync separator. timing is adjusted automatically for various video standards. the composite sync output follows video in sync pulses and a vertical sync pulse is output on the rising edge of the first vertical serration following the vertical pre-equalizing string. for non- standard vertical inputs, a default vertical pulse is output when the vertical signal stays low for longer than the vertical sync default delay time. the horizontal output gives horizontal timing with pre/post equalizing pulses. the use of two sync separators allows the user to send independent sync information for two signals to downstream devices. an example would be two video decoders or two adcs that are used in a pictur e-in-picture application. each sync separator is dedicated to its respective channel, sync separator a for channel a and sync separator b for channel b. it is important to note that the syncs for each channel cannot be muxed ont o the other channel. for example, hsync in a and vsync in a cannot be muxed to hsync out b and vsync out b. see the ?sync separator timing diagrams? beginning on page 32 for typical horizontal and vertical sync output timing. vertical sync a low-going vertical sync pulse is output during the start of the vertical cycle of the incomi ng video signal . the vertical cycle starts with a pre-equalizing phase of pulses with a duty cycle of about 93%, fo llowed by a vertical serration phase that has a duty cycle of about 15 %. vertical sync is clocked out of the isl59450 on the first rising edge during the vertical serration phase. in t he absence of vertical serration pulses, a vertical sync pulse will be forced out after the vertical sync default delay time, approximately 60s after the last falling edge of the vertical equalizing phase. horizontal sync the horizontal circuit senses the composite sync edges and produces the true horizontal pulses of nominal width 5s for standard definition ntsc signals. the pulse width of the hsync output changes as the line frequency of the input signal changes. for example, an ntsc input generates an hsync out with a pulse width of 5s; while a 720p hd video input generates an hsync out with a pulse width of 1.9s. the leading edge is triggered from the leading edge of the input hsync with the same propagation delay as composite sync. the half line pulses present in the input signal during vertical blanking are removed with an internal 2h line eliminator circuit. this is a circuit that inhibits horizontal output pulses until 75% of the line time is reached, then the horizontal output oper ation is enabled again. any signals present on the i/p signal after the true h sync will be ignored, thus the horizontal output will not be effected by macrovision copy protection. when there is a loss of sync, the horizontal sync output is held high. c set connect external capacitors from c set a and c set b to ground. the c set capacitor should be a x7r grade or better as the y5u general use capacitors may be too leaky and cause faulty operation. the c set capacitor should be very close to the c set a and c set b pins to reduce possible board leakage. 56nf is recommended. the c set capacitor rectifies a 5s pulse current and creates a voltage on c set . component: pr/pb (yprpb mode) v chroma x1 v chroma x2 v chroma x1 v chroma x2 component: pr/pb (rgb mode) v luma x1 v luma x2 v luma x1 v luma x2 table 2. suggested reference levels reference voltage (v) vtip in a0.5 vtip in b0.5 v luma x1 in a0.5 v luma x2 in a0.5 v luma x1 in b0.5 v luma x2 in b0.5 v chroma x1 in a1 v chroma x2 in a1 v chroma x1 in b1 v chroma x2 in b1 vslice in a0.6 vslice in b0.6 table 1. channel reference levels (continued) video output master mode slave mode gain 1 gain 2 gain 1 gain 2 isl59450
23 fn7510.0 february 14, 2008 the c set voltage is converted to bias current for h sync and v sync timing. internal control registers the isl59450 is initialized and controlled by a set of internal registers that define the operati ng parameters of the entire device. communication is established between the external controller and the isl59450 through a standard i 2 c host port interface, as described earlier. the register listing table on page 24 describes all of these registers. detailed i 2 c programming information for each register is described in ?isl59450 serial communications? on page 33. note: do not write to reserved registers. reserved bits in any register should be wri tten with 0s, unless otherwise noted. initialization it is recommended that the regist ers are initialized to 0x00 by toggling the reset pin low after powering the device. once the registers are initialized, set bit 0 of miscellaneous register 1 to one to engage the global enable and allow the various channels to be powered up. logic control signals reset is a 5v digital input, with 3.5v logic threshold and a 300k pull-down. tie to +5v for normal operation. taking reset to 0v and back to 5v initializes all data registers to 0x00. power-down is a digital input with 300k pull-down. when this pin is taken high, all analog circuitry is disabled to minimize power consumption. in power-down mode, the outputs are tri-stated while the i 2 c interface remains active and all register data is retained. crosstalk issues do not set any one input to both a and b channels if the references and modes for a and b are different. for example, do not send cv in 0 to both cv out a and cv out b if the references for channel a and channel b are different or if one channel is in slave mode while the other is in master mode. this could cause clamping conflicts and compromise performance. use the lowest bandwidth setting suitable for each application to minimize noise, aliasing, and crosstalk. see ?typical application curves? on page 19 and page 19. layout issues ? match channel-to-channel analog i/o trace lengths and layout symmetry. this will minimize propagation delay mismatches for s-video and component traces. ? all signal i/o lines should be routed over continuous ground planes (i.e. no split planes or pcb gaps under these lines). ? put the proper termination resi stors as close to the device as possible. ? when testing, use high quality connectors and cables, matching cable types and keep cable lengths to a minimum. ? decouple well using a minimum of 2 power supply decoupling capacitors (1000pf, 0.01f), placed as close to the devices as possible. vias between the capacitor and the device add unwanted inductance. larger capacitors can be farther away. power dissipation with the high output drive capabi lity of the isl59450, it is possible to exceed the +125c absolute maximum junction temperature under certain load current conditions. therefore, it is im portant to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. the maximum power dissipation allowed in a package is determined according to equation 1: where: t jmax = maximum junction temperature t amax = maximum ambient temperature ja = thermal resistance of the package the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the load, or: for sourcing use equation 2: for sinking use equation 3: where: v s = supply voltage i smax = maximum quiescent supply current v out = maximum output voltage of the application r load = load resistance tied to ground i load = load current pd max t jmax t amax ? ja -------------------------------------------- - = (eq. 1) pd max v s i smax v s v out ? () + v out r l --------------- - = (eq. 2) pd max v s i smax v out v s ? () + i load = (eq. 3) isl59450
24 fn7510.0 february 14, 2008 register listings isl59450 i 2 c control map data grey = read only, white = read/write i 2 c addr. function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 sync separator a sync output polarity reserved set to 0 enable reserved set to 0 sync input polarity sync type input select b1 input select b0 0x01 sync separator b sync output polarity reserved set to 0 enable reserved set to 0 sync input polarity sync type input select b1 input select b0 0x02 composite output a slave mode a low offset mode enable output amplifier gain filter disable input select b2 input select b1 input select b0 0x03 composite output b slave mode b low offset mode enable output amplifier gain filter disable input select b2 input select b1 input select b0 0x04 s-video output group a slave mode a low offset mode enable output amplifier gain filter disable reserved set to 0 input select b1 input select b0 0x05 s-video output group b slave mode b low offset mode enable output amplifier gain filter disable reserved set to 0 input select b1 input select b0 0x06 component video output group a slave mode a rgb mode enable output amplifier gain filter b1 filter b0 input select b1 input select b0 0x07 component video output group b slave mode b rgb mode enable output amplifier gain filter b1 filter b0 input select b1 input select b0 0x08 - 0x13 reserved ignore the contents of and do not write to these registers. 0 0 0 0 0 0 0 0 0x14 miscellaneous 1 s-video connected. field invert enable allows field output signal to be inverted when "sync output polarity" bit is set. global enable: 0: low power standby mode with outputs in high- impedance state, 1: powers up all internal reference s-video 3 connected s-video 2 connected s-video 1 connected s-video 0 connected reserved set to 0 reserved set to 0 field invert enable global enable 0x15 reserved ignore the contents of and do not write to these registers. reserved reserved reserved reserved reserved reserved reserved reserved 0x16 miscellaneous 2 component a low offset mode disable component a clamp disable s-video a clamp disable composite a clamp component b low offset mode disable component b clamp disable s-video b clamp disable composite b clamp isl59450
25 fn7510.0 february 14, 2008 register descriptions address register bit(s) function name description 0x00 sync separator a 1:0 input select a chooses the sync source for sync separator a to process. use these bits in conjunction with the sync type bit directly below. 00: component sog (channel a) 01: s-video sog (channel a) 10: composite sog (channel a) 11: external h and v or csync on h (channel a) 2 sync type a this bit must be set to the type of incoming sync. for all sog or csync signals, this bit should be set. 0: hsync is on hsynca, vsync is on vsynca 1: sog or csync on hsynca 3 sync input polarity a this bit must be set depending on the polarity of the incoming sync. 0: sog and active low external hsync/csync. 1: active high external, hsync/csync signal. this forces the internal polarity of the hsync signal to be correct for clamping. please note setting this bit also inverts the polarity of hsynca and vsynca outputs. see ?typical register settings? on page 31 for correct values. 4 reserved set this bit to 0. 5 enable a 0: sync separator a is disabled 1: sync separator a is enabled 6 reserved set this bit to 0. 7 sync output polarity a polarity of hsynca and vsynca outputs 0: active low 1: active high note: if the field invert enable bit (register 0x14b1) is set, fielda?s output will also be inverted when this bit is set. isl59450
26 fn7510.0 february 14, 2008 0x01 sync separator b 1:0 input select b chooses the sync source for sync separator b to process. use these bits in conjunction with the sync type bit directly below. 00: component sog (channel b) 01: s-video sog (channel b) 10: composite sog (channel b) 11: external h and v or csync on h (channel b) 2 sync type b this bit must be set to the type of incoming sync. for all sog or csync signals, this bit should be set. 0: hsync is on hsyncb, vsync is on vsyncb 1: sog or csync on hsyncb 3 sync input polarity b this bit must be set depending on the polarity of the incoming sync. 0: sog and active low external hsync/csync. 1: active high external, hsync/csync signal. this forces the internal polarity of the hsync signal to be correct for clamping. please note setting this bit also inverts the polarity of hsyncb and vsyncb outputs. see ?typical register settings? on page 31 for correct values. 4 reserved set this bit to 0. 5 enable b 0: sync separator b is disabled 1: sync separator b is enabled 6 reserved set this bit to 0. 7 sync output polarity b polarity of hsyncb and vsyncb outputs 0: active low 1: active high note: if the field invert enable bit (register 0x14b1) is set, fieldb?s output will also be inverted when this bit is set. 0x02 composite channel a 2:0 input select a 0: cvbs in 0 1: cvbs in 1 2: cvbs in 2 3: cvbs in 3 4: cvbs in 4 5: cvbs in 5 3 filter disable a 0: 7m hz smoothing filter 1: smoothing filter bypassed (40mhz bandwidth) 4 output amplifier gain a 0: x1 1: x2 5 enable a 0: disables (high-z) composite a output 1: enables composite output a 6 low offset mode a 0: normal mode 1: low offset mode slightly lowers the dc offset from input to output by increasing the maximum amount of clamp restore current from 130a to 270a . 7 slave mode a 0: sync tip dc-restore on selected channel (master mode) 1: dc-restore clamp timing slaved to sync separator a (slave mode) register descriptions (continued) address register bit(s) function name description isl59450
27 fn7510.0 february 14, 2008 0x03 composite channel b 2:0 input select b 0: cvbs in 0 1: cvbs in 1 2: cvbs in 2 3: cvbs in 3 4: cvbs in 4 5: cvbs in 5 3 filter disable b 0: 7m hz smoothing filter 1: smoothing filter bypassed (40mhz bandwidth) 4 output amplifier gain b 0: x1 1: x2 5 enable b 0: disables (high-z) composite b output 1: enables composite output b 6 low offset mode b 0: normal mode 1: low offset mode slightly lowers the dc offset from input to output by increasing the maximum amount of clamp restore current from 130a to 270a. 7 slave mode b 0: sync tip dc-restore on selected channel (master mode) 1: dc-restore clamp timing slaved to sync separator b (slave mode) 0x04 s-video channel a 1:0 input select a 0: svideo in 0 1: svideo in 1 2: svideo in 2 3: svideo in 3 2 reserved set this bit to 0 3 filter disable a 0: 10mhz smoothing filter 1: smoothing filter bypassed (40mhz bandwidth) 4 output amplifier gain a 0: x1 1: x2 5 enable a 0: disables (high-z) s-video a outputs 1: enables s-video a outputs 6 low offset mode a 0: normal mode 1: low offset mode slightly lowers the dc offset of the output by increasing the maximum amount of clamp restore current from 130a to 270a. 7 slave mode a 0: sync tip dc-restore on selected channel (master mode) 1: dc-restore clamp timing slaved to sync separator a (slave mode) register descriptions (continued) address register bit(s) function name description isl59450
28 fn7510.0 february 14, 2008 0x05 s-video channel b 1:0 input select b 0: svideo in 0 1: svideo in 1 2: svideo in 2 3: svideo in 3 2 reserved set this bit to 0 3 filter disable b 0: 10mhz smoothing filter 1: smoothing filter bypassed (40mhz bandwidth) 4 output amplifier gain b 0: x1 1: x2 5 enable b 0: disables (high-z) s-video b outputs 1: enables s-video b outputs 6 low offset mode b 0: normal mode 1: low offset mode slightly lowers the dc offset of the output by increasing the maximum amount of clamp restore current from 130a to 270a. 7 slave mode b 0: sync tip dc-restore on selected channel (master mode) 1: dc-restore clamp timing slaved to sync separator b (slave mode) 0x06 component channel a 1:0 input select a 0: ypbpr in 0 1: ypbpr in 1 2: ypbpr in 2 3: ypbpr in 3 3:2 filter select a 0: 10mhz smoothing filter 1: 20mhz smoothing filter 2: 36mhz smoothing filter 3: smoothing filter bypassed (250mhz bandwidth) 4 output amplifier gain a 0: x1 1: x2 5 enable a 0: disables (high-z) component a outputs 1: enables component a outputs 6 rgb mode a 0: ypbpr mode y clamps to vtip in a (master mode) y clamps to v luma x1/2 in a (slave mode) pb/pr clamps to v chroma x1/2 in a 1: rgb mode y clamps to vtip in a (master mode) y clamps to v luma x1/2 in a (slave mode) pb/pr clamps to v luma x1/2 in a 7 slave mode a 0: sync tip dc-restore on selected channel (master mode) 1: dc-restore clamp timing slaved to sync separator a (slave mode) register descriptions (continued) address register bit(s) function name description isl59450
29 fn7510.0 february 14, 2008 0x07 component channel b 1:0 input select b 0: ypbpr in 0 1: ypbpr in 1 2: ypbpr in 2 3: ypbpr in 3 3:2 filter select b 0: 10mhz smoothing filter 1: 20mhz smoothing filter 2: 36mhz smoothing filter 3: smoothing filter bypassed (250mhz bandwidth) 4 output amplifier gain b 0: x1 1: x2 5 enable b 0: disables (high-z) component b outputs 1: enables component b outputs 6 rgb mode b 0: ypbpr mode y clamps to vtip in b (master mode) y clamps to v luma x1/2 in b (slave mode) pb/pr clamps to v chroma x1/2 in b 1: rgb mode y clamps to vtip in b (master mode) y clamps to v luma x1/2 in b (slave mode) pb/pr clamps to v luma x1/2 in b 7 slave mode b 0: sync tip dc-restore on selected channel (master mode) 1: dc-restore clamp timing slaved to sync separator b (slave mode) 0x08-0x0b reserved (read only) 7:0 reserved reserved 0x0c-0x0d reserved 7:0 reserved write 0x00 to these registers 0x0e-0x11 reserved (read only) 7:0 reserved reserved 0x12-0x13 reserved 7:0 reserved write 0x00 to these registers 0x14 miscellaneous 1 (bits 4 thru 7 are read-only) 0 global enable 0: all outputs disabled 1: outputs enabled per their individual enable settings 1 field invert enable 0: the sync output polarity bit (sync separator) does not affect field polarity. 1: the sync output polarity bit (sync separator) inverts the field output. 2 reserved set this bit to 0 3 reserved set this bit to 0 4 s-video 0 connected 0: cable plugged in to s-video channel 0 1: nothing plugged in to s-video channel 0 5 s-video 1 connected 0: cable plugged in to s-video channel 1 1: nothing plugged in to s-video channel 1 6 s-video 2 connected 0: cable plugged in to s-video channel 2 1: nothing plugged in to s-video channel 2 7 s-video 3 connected 0: cable plugged in to s-video channel 3 1: nothing plugged in to s-video channel 3 0x15 reserved 7:0 reserved reserved register descriptions (continued) address register bit(s) function name description isl59450
30 fn7510.0 february 14, 2008 0x16 miscellaneous 2 0 disable composite b clamp this bit disables the dc-restore clamp for composite channel b. 0: composite a clamp enabled 1: composite a clamp disabled 1 disable s-video b clamp this bit disables the dc-restore clamp for the luma (y) of s-video channel b. disables the 1a pull-down currents for both y and c. does not disable the clamp for chroma channel unless in slave mode and sync separator. b = 0x25. 0: s-video a clamp enabled 1: s-video a clamp disabled 2 disable component b clamp this bit disables the dc-restore clamp for y/g of component channel b. disables the 1a pull-down currents for all three channels. does not disable the pull-up clamp for pr/r and pb/b unless in slave mode and sync separator. b = 0x24. 0: y component a clamp enabled 1: y component a clamp disabled 3 component b low offset mode 0: normal operation 1: dc-restore clamp has a lower offset. slightly lowers the dc offset of the component outputs by increasing the maximum amount of clamp restore current from 250a to 500a. 4 disable composite a clamp this bit disables the dc-restore clamp for composite channel a 0: composite a clamp enabled 1: composite a clamp disabled 5 disable s-video a clamp this bit disables the dc-restore clamp for the luma (y) of s-video channel a. disables the 1a pull-down currents for both y and c. does not disable the clamp for chroma channel unless in slave mode and sync separator. a = 0x25. 0: s-video a clamp enabled 1: s-video a clamp disabled 6 disable component a clamp this bit disables the dc-restore clamp for y/g of component channel a. disables the 1a pull-down currents for all three channels. does not disable the clamps for pr/r and pb/b unless in slave mode and sync separator. a = 0x24. 0: y component a clamp enabled 1: y component a clamp disabled 7 component a low offset mode 0: normal operation 1: dc-restore clamp has a lower offset. slightly lowers the dc offset of the component outputs by increasing the maximum amount of clamp restore current from 250a to 500a. register descriptions (continued) address register bit(s) function name description isl59450
31 fn7510.0 february 14, 2008 typical register settings register settings video type channel a register address channel b register address channel register value sync separator register value for all settings, miscellaneous 1 r egister (0x14) = 0xx1 and mi scellaneous 2 (0x16) = 0x00. composite 0 composite 0x02 0x03 0x30 0x00 composite 1 composite 0x02 0x03 0x31 0x00 composite 2 composite 0x02 0x03 0x32 0x00 composite 3 composite 0x02 0x03 0x33 0x00 composite 4 composite 0x02 0x03 0x34 0x00 composite 5 composite 0x02 0x03 0x35 0x00 s-video 1 s-video 0x04 0x05 0x30 0x00 s-video 2 s-video 0x04 0x05 0x31 0x00 s-video 3 s-video 0x04 0x05 0x32 0x00 s-video 4 s-video 0x04 0x05 0x33 0x00 component 0 component 0x06 0x07 0x3c 0x00 rgb + hv 0x06 0x07 0xfc 0x23 (active low sync in) 0xab (active high sync in) component 1 component 0x06 0x07 0x3d 0x00 rgb + hv 0x06 0x07 0xfd 0x23 (active low sync in) 0xab (active high sync in) component 2 component 0x06 0x07 0x3e 0x00 rgb + hv 0x06 0x07 0xfe 0x23 (active low sync in) 0xab (active high sync in) component 3 component 0x06 0x07 0x3f 0x00 rgb+hv 0x06 0x07 0xff 0x23 (active low sync in) 0xab (active high sync in) isl59450
32 fn7510.0 february 14, 2008 sync separator ntsc vertical timing sync separator ntsc horizontal timing 1 2 3 4 5 6 7 8 9 10 19 20 21 3h 3h 3h vertical blanking interval = 20h +h -h 1271s +63.5s -0s 1.5s 0.1s time 9 line vertical interval pre- equalizing pulse interval vertical sync pulse interval post- equalizing pulse interval h h sync interval start of field one h h 0.5h h ref subcarrier phase, color field one signal 1a. composite video input, field one signal 1b. vertical sync output signal 1c. horizontal sync output 280s notes: 2. the composite sync output reproduces all the video input sync pulses, with a propagation delay. 3. vertical sync leading edge is coincident with the first vertical serration pul se leading edge with a propagation delay. 4. horizontal sync output produces the true ?h? pulses of nominal width of 5s. it has the same delay as the composite sync. 50% sync tip v sync (sync tip voltage) v slice sync level color burst v blank (blanking level voltage) white level input dynamic range 0.5v to 2v video sync td hout t hout sync in h out conditions: v d = 3.3v, t a = +25c isl59450
33 fn7510.0 february 14, 2008 sync separator hsy nc timing for 720p isl59450 serial communications i 2 c overview the isl59450 uses a 2-wire i 2 c serial bus for communication with its host. scl is the serial clock line, driven by the host, and sda is the serial data line, which can be driven by all devices on the bus. sda is open drain to allow multiple devices to share the same bus simultaneously. communication is accomplished in three steps: 1. the host selects the isl 59450 with which it wishes to communicate. 2. the host writes the init ial isl59450 configuration register address it wishes to write to or read from. 3. the host writes to or reads from the isl59450?s configuration register. the isl59450?s internal address pointer auto increments, so to read registers 0x00 through 0x16, for example, one would write 0x00 in step two, then repeat step four 28 times, with each read returning the next register value. the isl59450 has a 7-bit address on the serial bus. the upper 6-bits are permanently set to 100010x, with the x determined by the state of the address pin (table 3). this allows two isl59450s to be independently controlled while sharing the same bus. the address pin has an internal pull-down resistor to pull the terminal low to set a zero. the bus is nominally inactive, with sda and scl high. communication begins when the host issues a start command by taking sda low while scl is high (figure 34). the isl59450 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. the host then transmits the 7-bit serial address plus a r/w bit, indicating if the next transaction will be a read (r/w = 1) or a write (r/w = 0). if the address transmitted matches that of any device on the bus, that device must respond with an acknowledge (figure 35). parameter description conditions typ unit td hout hout timing relative to input 200 ns t hout horizontal output width 5s conditions: v d = 3.3v t a = +25c syncin td hout t hout h out parameter description conditions typ @ 3.3v unit td hout hout timing relative to input 90 ns t hout horizontal output width 1.90 s table 3. i 2 c address options b7 b6 b5 b4 b3 b2 b1 b0 hex a6 (msb)a5a4a3a2a1 a0 (address) r/w 1 0 0 0 0 1 0 1/0 0x85/0x84 1 0 0 0 0 1 1 1/0 0x87/0x86 isl59450
34 fn7510.0 february 14, 2008 once the serial address has been transmitted and acknowledged, one or more bytes of information can be written to or read from the slave. communication with the selected device in the selected direction (read or write) is ended by a stop command, where sda rises while scl is high (figure 34), or a second start command, which is commonly used to reverse data direction without relinquishing the bus. data on the serial bus must be valid for the entire time scl is high (figure 36). to achieve this, data being written to the isl59450 is latched on a delayed version of the rising edge of scl. scl is delayed and de-glitched inside the isl59450 for three crystal clock periods (120ns for a 25mhz crystal) to eliminate spurious clock pulse s that could disrupt serial communication. when the contents of the isl59450 are being read, the sda line is updated after the falling edge of scl, delayed and de-glitched in the same manner. configuration register write figure 37 shows two views of the steps necessary to write one or more words to the configuration register. configuration register read figure 38 shows two views of the steps necessary to read one or more words from the configuration register. scl sda start stop figure 34. valid start and stop conditions scl from host data output from transmitter data output from receiver 8 1 9 start acknowledge figure 35. acknowledge response from receiver scl sda data stable data change data stable figure 36. valid data changes on the sda bus isl59450
35 fn7510.0 february 14, 2008 d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 isl59450 register data write(s) this is the data to be written to the isl59450?s configuration register. note: the isl59450?s configuration register?s address pointer auto increments after each data write. repeat this step to write multiple sequential bytes of data to the configuration register. a6 a5 1 000 0 0 r/w isl59450 register address write this is the address of the isl59450? s configuration register that the following byte will be written to. isl59450 serial address figure 37. configuration register write start command stop command (repeat if desired) signals the beginning of serial i/o signals the ending of serial i/o s t a r t s t o p data write* register address serial bus address a c k aaaaaaaa a c k dddddddd a c k aaaaaaa0 * the data write step may be repeated to write to the isl59450?s configuration register sequentially, beginning at the register address written in the previous step. sda bus signals from the isl59450 signals from the host 1 addr isl59450 device select address write the first 7 bits of the first byte select the isl59450 on the 2-wire bus at the address set by the address pin. r/w = 0, indicating the next transaction will be a write. isl59450
36 fn7510.0 february 14, 2008 figure 38. configuration register read a0 a7 a2 a4 a3 a1 a6 a5 1 00 1 0 0 r/w isl59450 register address write this sets the initial address of the isl59450?s configuration register for subsequent reading. isl59450 serial bus start command signals the beginning of serial i/o isl59450 serial bus address read this is the 7-bit address of the isl59450 on the 2-wire bus. the address is 0x85 if pin 92 is low, 0x87 if pin 92 is high. r/w = 1, indicating next transacti on(s) will be a read. d7 d6 d5 d2 d4 d3 d1 d0 isl59450 register data read(s) this is the data read from the isl59450?s configuration register. note: the isl59450?s configurati on register?s address pointer auto increments after each data read. repeat this step to read multiple sequential bytes of data from the configuration register. 1 00 1 1 0 r/w isl59450 serial bus start command stop command (repeat if desired) ends the previous transaction and starts a new one signals the ending of serial i/o s t a r t s t o p data read* sda bus signals from the isl59450 signals from the host register address serial bus address a c k aaaaaaaa a c k dddddddd a c k aaaaaaa0 * the data read step may be repeated to read from the isl59450?s configuration register sequentially, beginning at the register address written in the two previous steps. r e s t a r t serial bus address a c k aaaaaaa1 isl59450 device select address write the first 7 bits of the first byte select the isl59450 on the 2-wire bus at the address set by the address pin. r/w = 0, indicating the next transaction will be a write. address 0 address 0 isl59450
37 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7510.0 february 14, 2008 isl59450 metric plastic quad flatpack packages (mqfp) y all around drop in heat spreader 4 stand points may be exposed pin 1 id d1 d e e1 18.500 ref 12.500 ref c0.600x0.350 (4x) 19.870 0.100 20.000 0.100 (e1) 13.870 0.100 14.000 0.100 a a 1 2 all around (d1) 1 1 section a-a t b b1 t1 ccc c a2 a a1 r0.13 min r0.25 typ c ddd c m l1 0 min 0.200 min t gauge plane detail y 0.13~0.30 128 1 l b e seating plane 0.25 base do not try to connect electrically mdp0055 14x20mm 128 lead mqfp (with and without heat spreader) 3.2mm footprint symbol dimensions ( millimeters) remarks a max 3.40 overall height a1 0.250~0.500 standoff a2 2.750 0.250 package thickness 0~7 foot angle b 0.220 0.050 lead width b1 0.200 0.030 lead base metal width d 17.200 0.250 lead tip to tip d1 14.000 0.100 package length e 23.200 0.250 lead tip to tip e1 20.000 0.100 package width e 0.500 base lead pitch l 0.880 0.150 foot length l1 1.600 ref. lead length t 0.170 0.060 frame thickness t1 0.152 0.040 frame base metal thickness ccc 0.100 foot coplanarity ddd 0.100 foot position rev. 2 2/07 notes: 1. general tolerance: distance 0.100, angle +2.5. 2. matte finish on package body surface except ejection and pin 1 marking (ra 0.8~2.0um). 3. all molded body sharp corner radii unless otherwise specified (max ro.200). 4. package/leadframe misalignment (x, y): max. 0.127 5. top/bottom misalignment (x, y): max. 0.127 6. drawing does not include plastic or metal protrusion or cutting burr. 7. compliant to jedec ms-022. 1 1 1 1 1 2

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